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Field-Programmable Logic and Applications

13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings

This book constitutes the refereed proceedings of the 13th International Conference on Field-Programmable Logic and Applications, FPL 2003, held in Lisbon, Portugal in September 2003. The 90 revised full papers and 56 revised poster papers presented were carefully reviewed and selected from 216 submissions. The papers are organized in topical sections on technologies and trends, communications applications, high level design tools, reconfigurable architecture, cryptographic applications, multi-context FPGAs, low-power issues, run-time reconfiguration, compilation tools, asynchronous techniques, bio-related applications, codesign, reconfigurable fabrics, image processing applications, SAT techniques, application-specific architectures, DSP applications, dynamic reconfiguration, SoC architectures, emulation, cache design, arithmetic, bio-inspired design, SoC design, cellular applications, fault analysis, and network applications.

13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003,
Proceedings Peter Y.K. Cheung, Georg A. Constantinides Jose T. de Sousa. An
Algorithm Designer's Workbench for Platform FPGAs⋆ Sumit Mohanty and Viktor
K. Prasanna Electrical Engineering Systems, University of Southern California,
CA, USA, {smohanty ...

Field-Programmable Logic and Applications

5th International Workshop, FPL '95, Oxford, United Kingdom, August 29 - September 1, 1995. Proceedings

This volume constitutes the proceedings of the Fifth International Workshop on Field-Programmable Logic and Its Applications, FPL '95, held in Oxford, UK in August/September 1995. The volume presents 46 full revised papers carefully selected by the program committee from a large number and wide range of submissions. The papers document the progress achieved since the predecessor conference (see LNCS 849). They are organized in sections on architectures, platforms, tools, arithmetic and signal processing, embedded systems and other applications, and reconfigurable design and models.

The REDOC III algorithm for data ciphering is a potential replacement for DES.
This paper looks at ways of customising the algorithm to increase security without
reducing ciphering speed. Many valuable modifications are possible if
reconfigurable hardware is used.